The invention relates to memory devices, and, specifically, relates to three-dimensional memory devices.
Generally, non-volatile memory devices may implement various design features. One of them includes a so-called SONOS (silicon-oxide-nitride-oxide-silicon) design, which may use a thin tunnel oxide to allow direct-tunneling erase. FIG. 1 illustrates an example of a SONOS non-volatile memory device. Referring to FIG. 1, the memory device may include a source region 10 and a drain region 12, an active or channel region 14, a gate dielectric layer 16 over the active region 14, and a gate 18 over the gate dielectric layer 16. Generally, the active region 14 may be formed adjacent to, such as over or between, the source and drain regions 10 and 12. And the gate dielectric 16 may have an “ONO” structure having two silicon oxide layers with a silicon nitride layer in-between.
Conventional memory devices provide memory cells or storage units in a two-dimensional design to facilitate operation. However, with the development of portable and many other devices requiring a large number of memory cells within a limited chip space, there is a need for non-volatile memory devices that can provide more memory cells within a limited space.